Frequency difference detector

ABSTRACT

A system for detecting a frequency difference between a known reference frequency and an unknown frequency wherein both frequencies are delayed and respectively applied to a bistable element whose output state is utilized to control respectively a pair of AND logic elements which also receive signals as inputs respectively in response to the undelayed frequencies, an output from either of the AND elements being indicative that a frequency difference exists and the direction of the difference.

United States Patent Pattantyus [4 1 May 16, 1972 [54] FREQUENCYDIFFERENCE DETECTOR [72] inventor: Tamas l. Pattantyus, Pittsburgh, Pa.

[73] Assignee: Westinghouse Electric Corporation, Pittsburgh, Pa.

22 Filed: Oct. 24, 1969 211 Appl.No.: 869,268-

[56] References Cited UNITED STATES PATENTS 3,328,688 6/1967 Brooks..328/1 33 3,382,376 5/1968 Sowden .....307/233 3,441,342 4/1969 Ball..328/134 3,509,476 4/1970 Roth ..328/1 41 3,100,294 8/1963 Dryden..307/239 Primary Examiner-Donald D. Forrer Assistant Examiner-R. E.Hart Attorney-F. H. Henson, C. F. Renz and A. S. Oddi [57] ABSTRACT Asystem for detecting a frequency difference between a known referencefrequency and an unknown frequency wherein both frequencies are delayedand respectively applied to a bistable element whoseoutput state isutilized to control respectively a pair of AND logic elements which alsoreceive signals as inputs respectively in response to the undelayedfrequencies, an output from either of the AND elements being indicativethat a frequency difference exists and the direction of the difference.

REFERENCE R FREQUENCY SOURCE A DELAY TI 1 MoNo- STABLE 5 Claims, 2Drawing Figures UNKNOWN FREQUENCY 1 SOURCE DELAY l Tl MONO M X R /FFSTABLE PAIEIII'EDIIIIY I 6 Ian 3,563,88

v REFERENCE VR UNKNOWN /U FREQUENCY DX FREQUENCY SOURCE I SOURCE A DELAYDELAY B TI TI MoNo- M MoNo- /Mx STABLE s /FF STABLE FLIP FLOP Y Y .Q Q 5I I A AND AX FIG I Ar H fr fx fr fx II I2 I3 I4 I5 we I? 18 I9 No III N2N3 II4II5 IICNYIIB QI L o2- 03+ 04 05 Ius I a7 I Tl I I Tr b2\ I b3 b4b5 i I l l l I I I I I TI TX I I g Y I I I I l O I I I I I I I I I I I I'I I 'I D I l I I I I I I I FIG. 2

WITNE s sEs INVENTOR Tomas I. Pclfionryus JIM II. BY U 1 a AT oRNEY 1.Field of the Invention The present invention relates to frequencydifference detector systems and, more particularly, to such systems foruse in digital applications wherein the direction of the frequencydifference is also desired.

. 2. Discussion of the Prior Art In many control applications, such ascontrolling the recording of video information on a magnetic recordingdisc, it is highly desirable to have an indication that a frequencydifference exists between a known reference signal and an unknownfrequency signal. It is also desirable to have an indication of thedirection of the difference, that is, is the unknown frequency higher orlower in frequency than the reference frequency eventhough the absolutemagnitude of the frequency difference is not required. Various frequencydetection systems have been devised as shown, for example, in U.S. Pat.Nos. 3,235,800, 3,328,688, and 3,382,376. These patents, beingrepresentative of the prior art, have one common feature of utilizingtwo or more bistable elements (flip-flops) for detecting the frequencydifference between a reference .and an unknown frequency. Therequirements for multiple bistable elements thus necessitates arelatively complex and expensive system for performing the frequencydifference detection function and can hence result in a relativelyexpensive design.

Therefore, it'would be highly desirable if a frequency detection systemwere provided utilizing a minimum number of bistable elements and otherrelatively simple logic elements for providing the frequency detectionfunction, while additionally providing a system capable of detectingvery small frequency differences betweenthe reference frequency and theunknown frequency on the order of 0.03 percent of the referencefrequency.

SUMMARY OF THE INVENTION BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is ablock diagram of the frequency difference detection system of thepresent invention; and

FIG. 2 is a waveform diagram including curves A through H which areutilized in explaining the operation of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the drawing, thesystem of FIG. 1 is operative to detect a frequency difference between areference frequency fr and an unknown frequency ft. The referencefrequency fr is derived from a reference frequency source R whose outputis designated as A and is shown in Curve A of FIG. 2. The unknownfrequency fx is derived from an unknown frequency source U whose outputis indicated as B and is shown in Curve B of FIG. 2. The outputs A andB, as illustrated in the respective curves A and B of FIG. 2, are shownto be very narrow pulses having equal amplitudes. The originating sourcefor the reference and unknown frequency may of course typically comprisesquare or rectangular waveforms having varying amplitudes. Thesewaveforms may be processed by limiting and differentiating either theleading or trailing edges of the waveforms to develop the amplitudelimited, very narrow pulse waveform as shown in Curves A and B.

The output A of the reference frequency source R thus has a referencefrequency fr with a reference time period Tr between respective pulsesthereof, and the output B of the unknown frequency source U has anunknown frequency fx with an unknown time period Tx between therespective pulses thereof. For purposes of explanation, the referencefrequency fr is shown to be greater than the unknown frequency fx in theexample shown in the curves of FIG. 2. As indicated in Curve A thewaveform includes a plurality of reference pulses a. These pulses areapplied to a time delay element Dr which has a time delay Tl. Thus thepulses appear at the output of the delay Dr after a time delay of T1.The B- output comprises a plurality of pulses b and are supplied to asimilar delay element Dx which also has a time delay Tl wherein thepulses b of the curve B are delayed by a time period T1. The output ofthe reference delay Dr is applied to the set input of a bistable elementcomprising a flip-flop FF and the output of the delay D): is applied tothe reset input of the flip-flop FF. The flip-flop FF comprises the onlybistable element within the frequency detection system of the presentinvention.

The flip-flop FF has complementary outputs Y and V as indicated in FIG.2. In the reset condition of the flip-flop the Y output is a ZERO andthe complementary ?-output is a ONE. The Y- and Y-outputs of theflip-flop FF are shown in Curves C and D, respectively. The C output ofthe flip-flop FF is applied as one input to an AND logic circuit Ar andthe D-output which is the complement of the C-output, is applied as oneinput to an AND logic circuit Ax.

The reference output A of the reference frequency source R is alsoapplied in an undelayed manner to a monostable element Mr which providesa pulse output E such as shown in curve E of FIG. 2 in response to therespective pulse signals from curve A. The monostable Mr is designed tosupply output pulses of a time duration T2 which is shorter than thetime delay T1 of the delay elements Dr and Dx The output B of theunknown frequency source U is applied directly to a monostable elementMx, which is similar to the monostable Mr, and which supplies a pulseoutput F such as shown in curve F of FIG. 2 comprising pulses having apulse width T2.

The output E of the monostable Mr is supplied at the second input .tothe AND Ar, and the output F of the monostable Mx supplies the secondinput to the AND Ax. The respective outputs G andI-I of the AND logicelement Ar and Ax are shown in curves G and H, respectively, of FIG. 2.

At a time :1 the monostable Mr supplies an output pulse E in response tothe reference pulse a1, and the output E is applied to the AND Ar.However, since the flip-flop output C is at a ZERO state, the AND Ardoes not supply an output G. Since at the time 11, no B-pulse output issupplied by the unknown frequency source U, the monostable Mx does notsupply an output F and therefore the AND A): supplies no output at itsoutput H.

At a time :2, which is after a time delay Tl from the occurrence of thetime 11, the pulse a1 appears at the output of the delay Dr to provide aset input to the flip-flop FF which causes the flip-flop to reverseoutput states as shown in curves C and D, with the Y-output going to aONE and the V output going to ZERO. The ONE output appearing at theC-input to the AND Ar, however, does not permit the AND Ar to provide aG-output since the Einput thereto prior to the time 12 has reverted to aZERO state.

Approximately at the time 12 an unknown frequency pulse bl occurs whichcauses the monostable M): to output a pulse having a time duration of T2as shown in Curve F. However, since the D-output of the flip-flop at thetime 12 has been changed to a ZERO output, the AND Ax does not providean H-output at this time. After a time delay T] as determined by thedelay element Dx the flip-flop FF receives a reset input in response tothe delayed pulse bl so that the output states are changed with theY-output going to a ZERO and the ?-output going to a ONE. However, dueto the time delay T1 the AND Ax does not supply an output in that themonostable output F has terminated by the end of the time delay at thetime :3.

At a time :4 a reference pulse a2 occurs causing the monostable Mrtoprovide an output E. The AND Ar, however, C from the flip-flop FF. Afterthe flip-flop FF receives a set input from the delay Dr which causes theflipflop to change output states with the Y-output going to a ONE andthe ?-output going to a ZERO. At a time t6 a pulse bl occurs in the B-waveforrn which causes the monostable Mx to output a pulse as shown inCurve F. After the time delay T1, at a time :7, the delay Dx supplies areset input to the flip-flop FF so that the Y-output goes to a ZERO andthe Y goes to a ONE output. Accordingly, no output H is supplied by theAND Ax at this time. At the time t7 an output pulse a3 is provided bythe reference frequency source R which causes the monostable Mrto supplyan output E. However, the C-output of the flipfiop FF is at a ZEROstate, therefore, the AND Ar does not supply an output at this time.After the time delay T1 caused by the delay Dr, the flip-flop FF goes toits set state with the Y- output going to a ONE and the ?-output goingto a ZERO at the time :8.

At the time :9 the reference frequency source R supplies a referencepulse 04, which it should be noted occurs before the next unknownfrequency pulse b3 occurs, as shown in Curve B which does not occuruntil the time :10. The period Tr between the various pulses of theoutput A is thus shorter than the period Tx between the pulses of theoutput B.

At the time 79 in response to the reference pulse a4 the monostable Mrsupplies an output E to the AND Ar. The other input to the AND Ar isalso a ONE since the flip-flop FF has remained in the output state wherethe C-output is a ONE and the D-output is a ZERO since the time :8.Hence with the coincidence of monostable output E and the C-output fromthe flip-flop FF, the AND Ar supplies a G-output at the time t9 which isindicative of a frequency difference between the reference frequency frand the unknown frequency fx and also demonstrates the fact that thereference frequency fr is a higher frequency than the unknown frequencyfx.

After a time delay Tl caused by the delay Dr a set input is applied tothe flip-flop FF; however, since the flip-flop is already in its setoutput state this pulse will not cause the flipflop to change outputstates. At approximately the time 110 the pulse b3 from the unknownfrequency source U occurs which causes the monostable Mar to supplypulse output F to the AND Ax. However, with the flip-flop output 3 beingat a ZERO, the AND Ax does not supply an H-output. After a time delay T1from the time :10 when the pulse b3 occurred, the delay Dx will supply areset input to the flip-flop FF which will cause the outputs thereof torevert with the Y-output being a ZERO and the ?-output being a ONE.

At the time tll the next reference pulse a5 occurs which causes themonostable Mr to supply an E-output to the AND Ar. However, with theflip-flop in the indicated state, no output G will be provided at thetime 11 1. After a time delay T1 caused by the delay Dr occurring, at atime :12, a set input will be provided to the flip'flop FF which willcause the flip-flop to change output states with the Y-output going to aONE and the Y-output going to a ZERO.

At a time :13 a pulse b4 is provided by the unknown frequency source Uwhich causes the monostable Mx to output a pulse F. However, theD-output of the flip-flip FF at this time prevents an H-output frombeing supplied by the AND Ax. At a time I14 the delay Dx supplies areset input to the flip-flop FF causing it to change output states withthe C-output going to a ZERO and the D-output going to a ONE. Atapproximately the time tl4 a reference pulse a6 is supplied by thereference source R which causes the monostable Mr to supply an output Eand after a time delay T1 supplies a set input to the flip-flop FF viathe delay Dr which causes the output C of the flip-flop FF to go to aONE and the output D to go to a ZERO at a time 115.

At a time :16, which it should be noted is before the next output pulseb5 of the unknown frequency source U occurs at a time 117, a referencepulse a7 occurs causing the monostable Mr to supply an output E to theAND Ar which already has a ONE input from the output C of the flip-flopFF already applied to the other input thereto. Thus an output G issupplied from the AND Ar being indicative that the reference frequencyfr is at a higher frequency than the unknown frequency fx.

The flip-flop FF remains in the output state as indicated at the timetl6 until a time r18, which is a time period Tl later than the time 117at which the b5 pulse appears. The operation of the frequency detectionsystem thus continues as described with an output G being provided bythe AND Ar whenever two pulses a in the output A occur before succeedingpulses b of the output B occur.

The system operates in an analogous fashion should the unknown frequencyfx be higher than the reference frequency fr. In this instance the ANDAx would supply an output H whenever two of the unknown frequency pulsesb occurred between succeeding of the reference pulses a. It can thus beseen that the system functions through the use of only the singleflip-flop FF, the two time delays Dr and Dx, the two monostables Mr andMr and the two AND elements Ar and Ax. The flip-flop FF operates tocontrol whether or not the respective AND elements Ar or A): permits theoutput of the respective monostables Mr or Mx to be translated throughthe AND at the occurrence of a reference pulse or an unknown frequencypulse.

From the following analysis it may be seen that the present system hashigh resolving accuracy for detecting differences between the referencefrequency for an unknown frequency fx, particularly at relatively lowfrequency levels in the low KHZ. range. Considering the followingequation relating the periods of the reference and unknown frequenciesand taking into account the time delay T1 and any known time jitterbetween the reference and unknown periods it may be established:

Tx Tr sec.

10 1.0003 10 3 sec.

fr fx 1/10 (l/l.0003 10 fr fx 0.0003 10 fr fx 0.0003 fr it may thus beseen that taking the above defined parameters that the minimumdetectable frequency difference between the reference frequency fr andthe unknown frequency fx is 0.03 percent of the reference frequency or0.3 Hz. at 1,000 Hz. Hence it may be understood that the resolvingaccuracy of the proposed system is quite high while utilizing only thesingle bistable element FF and the other simple logic components asdescribed above with respect to FIG. 1.

I claim as my invention:

1. In a system for detecting a frequency difference and direction ofdifference between a reference signal having a known frequency and anunknown signal having an unknown frequency, the combination of:

monostable means for providing first and second monostable outputs inresponse to said reference and unknown signals respectively;

delay means for responding to the presence of each of said reference andunknown signals by similarly delaying each of said reference and unknownsignals respectively;

a two condition bistable means having first and second inputs and firstand second outputs, the delayed reference and unknown signals beingapplied input signals to said first and second inputs respectively, thepresence of an input signal at said first input assuring a first outputcondition at said first output and the presence of an input signal 2.The combination of claim 1 wherein: said first and second monostableoutputs have predetermined time durations,

the period of delay of said reference and unknown signals by saiddelaying means exceeding said predetennined time durations.

3. The combination of claim 2 wherein: said bistable means comprises aflip-flop element having a set and a reset input, the delayed referencesignal being applied to said set input and the delayed unknown signalbeing applied to the reset input,

said flip-flop element being non-responsive to inputs applied to eitherthe set or reset input until a reset or set input respectively isreceived.

4. The combination of claim 3 wherein:

said logic means includes a first AND circuit for receiving said firstmonostable output and said first output condition defining that saidfirst predetermined relationship is that said known frequency exceedssaid unknown frequency, and a second AND circuit for receiving saidsecond monostable output and said second output condition defining thatsaid unknown frequency exceeds said known frequency.

5. The combination of claim 4 wherein:

said monostable means includes first and second monostable elements forproviding respectively said first and second monostable outputs havingsubstantially equal time durations,

said delay means includes first and second delay elements for delayingrespectively said reference and unknown signals by said predeterminedtime delay.

* a s a a:

1. In a system for detecting a frequency difference and direction ofdifference between a reference signal having a known frequency and anunknown signal having an unknown frequency, the combination of:monostable means for providing first and second monostable outputs inresponse to said reference and unknown signals respectively; delay meansfor responding to the presence of each of said reference and unknownsignals by similarly delaying each of said reference and unknown signalsrespectively; a two condition bistable means having first and secondinputs and first and second outputs, the delayed reference and unknownsignals being applied input signals to said first and second inputsrespectively, the presence of an input signal at said first inputassuring a first output condition at said first output and the presenceof an input signal at said second input assuring a second outputcondition at said second output; and logic means responsive to saidfirst monostable output and said first output condition of said bistablemeans to provide a first detection output when said known and unknownfrequencies have a first predetermined relationship therebetween andresponsive to said second monostable output and said second outputcondition to provide a second detection output when said known andunknown frequencies have a second predetermined relationshiptherebetween.
 2. The combination of claim 1 wherein: said first andsecond monostable outputs have predetermined time durations, the periodof delay of said reference and unknown signals by said delaying meansexceeding said predetermined time durations.
 3. The combination of claim2 wherein: said bistable means comprises a flip-flop element having aset and a reset input, the delayed reference signal being applied tosaid set input and the delayed unknown signal being applied to the resetinput, said fLip-flop element being non-responsive to inputs applied toeither the set or reset input until a reset or set input respectively isreceived.
 4. The combination of claim 3 wherein: said logic meansincludes a first AND circuit for receiving said first monostable outputand said first output condition defining that said first predeterminedrelationship is that said known frequency exceeds said unknownfrequency, and a second AND circuit for receiving said second monostableoutput and said second output condition defining that said unknownfrequency exceeds said known frequency.
 5. The combination of claim 4wherein: said monostable means includes first and second monostableelements for providing respectively said first and second monostableoutputs having substantially equal time durations, said delay meansincludes first and second delay elements for delaying respectively saidreference and unknown signals by said predetermined time delay.